In order to achieve higher data throughput over a communication bus, a device can employ faster or wider buses, or both. A one-channel serializer/deserializer (SerDes) can be employed as a one-bit bus. In order to obtain the desired data throughput, multiple SerDes circuits are often employed in parallel. Each SerDes circuit typically has its own phase locked loop (PLL) circuit, and the PLLs on the multiple parallel SerDes circuits must operate synchronously. In addition, synchronization between different SerDes circuits at the transmitter is also desirable, because it simplifies data assembly at the receiver end.
A number of techniques have been proposed or suggested for maintaining synchronization among the multiple parallel SerDes circuits. For example, a reference clock that is external to the integrated circuit containing the multiple SerDes circuits has been used to synchronize the various PLLs on the multiple SerDes circuits. This technique, however, only supports synchronization at the full data rate of the reference clock. For different data rate applications, a different crystal oscillator is required to generate a reference clock associated with each data rate, thus increasing the cost of the system design.
A need therefore exists for improved methods and apparatus for maintaining channel synchronization among a plurality of SerDes circuits for such high data throughput applications.